A simple 4 G-bit DRAM technology utilizing high-aspect-ratio pillars for cell-capacitors and peripheral-vias simultaneously fabricated

A simple high-aspect-ratio pillar capacitor is realized for COB type STC cells for 4 Gbit DRAMs. The cell area is 0.21 /spl mu/m/sup 2/ with a design rule of 0.15 /spl mu/m. The high-aspect-ratio vias in the peripheral region due to the capacitor height are formed by via-pillars that are fabricated simultaneously with capacitor-pillars, resulting in keeping the surface flat for multiple-layer metal interconnections. The well-established ON dielectric film can be used by the high-aspect-ratio pillar capacitors instead of complicated structures such as cylindrical capacitors or unstable dielectrics such as BST. A pillar height of 1.5 /spl mu/m results in a storage capacitance of 17 fF/cell and a leakage-current of 0.058 fA/cell for ON dielectric film with an oxide equivalent thickness toxeq of 4.1 nm. The ON film is formed by oxidizing Si/sub 3/N/sub 4/ film at a low temperature of 650/spl deg/C and a high pressure of 25 atm. in steam. This process architecture fully utilizes the self-aligned process: a self-aligned contact etching of source and drain windows, a self-aligned elevated source and drain by polysilicon damascene, a self-aligned Ti silicidation of the surface of source and drain, a self-aligned plug to Si/sub 3/N/sub 4/ encapsulated bit-lines, a self-aligned patterning of capacitor plate-electrodes, and a self-aligned formation of metal contacts for peripheral vias and storage nodes. The silicided elevated source/drain and flat surface make this device structure suitable for merged DRAM/logic of the 4 Gbit DRAM era.