A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications

High performance 0.1 /spl mu/m (physical) gate length CMOS with 30 /spl Aring/ gate dielectric (C-V: gate accumulated at V/sub gb/=-3 V) is demonstrated at 1.0 V-1.5 V. Scaling to 0.1 /spl mu/m L/sub gate/ CMOS is described. At 1.5 V, nMOS strong and nominal I/sub drive/=757 and 700 /spl mu/A//spl mu/m, and pMOS strong and nominal I/sub drive/=337 and 300 /spl mu/A//spl mu/m. For high performance at 1.0 V, n- and pMOS are designed with low V/sub T/ and higher I/sub off/ (100 nA//spl mu/m at L/sub g//sup min/). At 1 V, nMOS strong and nominal I/sub drive/ is 516 and 473 /spl mu/A//spl mu/m; pMOS strong and nominal I/sub drive/ is 220 and 188 /spl mu/A//spl mu/m. Benchmarking to FOM and CV/I metrics is performed for this 1.0-1.5 V, 0.1 /spl mu/m node and prior 1.8-1.5 V, 0.18 /spl mu/m nodes. Present 1.5 V, 0.1 /spl mu/m CMOS (as well as our recently reported 1.8-1.5 V, 0.18 /spl mu/m CMOS) has FOM and CV/I values better than the literature trend. The FOM at V/sub DD/=1.0 V (max I/sub off/=100 nA//spl mu/m) is the same as the 1.5 V FOM (max I/sub off/=1 nA//spl mu/m).