An RF sampling downconversion filter for a receiver front-end

Darius Jakonis,Kalle Folkesson,Christer Svensson,Jerzy Dabrowski, Pontus Eriksson

Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium（2004）

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摘要

An integrable front-end architecture for WLAN applications in the 2.4 GHz band is described in this paper. It is based on a multi-functional switched-capacitor block, which performs RF sampling, quadrature downconversion to IF, tunable IF filtering, downconversion to baseband, and sampling rate decimation. The proposed RF sampling downconversion filter is designed in a 0.18-μm CMOS technology. In the downconverted channel band the anti-alias suppression is more than 26 dB. The signal gain is 8 dB, the noise figure is 22 dB, and the IIP3 is at +11 dBm. The image rejection is better than 66 dB. Without the clock generation block the sampling mixer and downconversion filter consume 2.9 mW power.

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关键词

cmos analogue integrated circuits,uhf filters,uhf integrated circuits,uhf mixers,integrated circuit design,radio receivers,sample and hold circuits,switched capacitor filters,wireless lan,0.18 micron,2.4 ghz,2.9 mw,22 db,8 db,cmos technology,if filtering,rf sampling downconversion filter,wlan,anti-alias suppression,image rejection,multifunctional switched capacitor filter,receiver front end architecture,sampling mixer,sampling rate decimation,filtering,gain,sampling methods,circuit switched,front end,switched capacitor,noise figure,baseband,indexing terms,radio frequency

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