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45Nm Node Planar-Soi Technology with 0.296 /spl Mu/m/sup 2/ 6T-SRAM Cell

FL Yang,CC Huang,TX Chung,HY Chen,CY Chang,HW Chen,DH Lee,SD Liu,KH Chen,CK Wen,SM Cheng,CT Yang, LW Kung, CL Lee,YJ Chou,FJ Liang,LH Shiu,JW You,KC Shu,BC Chang,JJ Shin,CK Chen,TS Gau,PW Wang,BW Chan,PF Hsu,JH Shieh,SKH Fung,CH Diaz,CMM Wu,YC See,BJ Lin,MS Liang,JYC Sun,CM Hu

2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS（2004）

Cited 6|Views4
Key words
MOSFET,SRAM chips,semiconductor device noise,silicon-on-insulator,0.296 μm2 6T-SRAM cell,0.6 V,120 mV,130 nm,140 nm,45 nm,45nm node planar-SOI technology,N-FET,P-FET
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