0.25 Micrometre Smart Power Technology Optimised For Wireless And Consumer Applications

R Zhu,V Parthasarathy,V Khemka,A Bose,T Roggenbauer, G Lee, B Baumert,P Hui,P Rodriquez, D Collins

Circuits, Devices and Systems, IEE Proceedings -（2004）

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Abstract

In this paper, simultaneous optimisation of 4.5-5.5V N and PMOS devices, 20-30V NLDMOS, and NPN and PNP bipolar devices in a 0.25 mum smart power technology for portable wireless and consumer applications is discussed. With the addition of two designated wells, ultra-low resistance N and PMOS devices with good analogue characteristics, best in class 30 V NLDMOS, and integrated high performance NPN and PNP bipolar devices are demonstrated. Practical implementation of a high voltage, isolated diode using an existing device is also discussed and demonstrated.

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Key words

anodes,electron emission,insulated gate bipolar transistors,600 V,P-buffer layer,anode design,ion implantations,n-buffer dose,n-buffer layer,p-emitter dose,p-emitter injection efficiency,p-type layer,power loss,punch through insulated gate bipolar transistor,tail current,tail loss,thin wafer PT-IGBT,transparent P-emitter,turn-off waveforms oscillation

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