A 75mW 10bit 120MSample/s parallel pipeline ADC
european solid-state circuits conference（2003）
Abstract
This paper describes a low-power high-speed parallel pipeline ADC. The thorough use of digital calibration and the pseudo-differential pipeline ADC architecture allow to realize the low-power design of high-speed ADC's. Capacitor mismatch, gain and offset errors are measured by a technique using INL plot, without any modification to ADC core. A prototype ADC with the error correction logic is fabricated in 0.3 µm 2-poly 3-metal CMOS technology. The 10bit 120M Sample/s ADC achieves 0.14LSB of DNL and 0.8LSB of INL with very low- power dissipation of 75mW at 2V. 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5
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Key words
CMOS logic circuits,analogue-digital conversion,integrated circuit design,low-power electronics,parallel architectures,pipeline processing,0.3 micron,10 bits,2 V,75 mW,ADC core,CMOS technology,INL plot,analog-to-digital converter,capacitor mismatch,digital calibration,error correction logic,high-speed ADC,low-power ADC,offset errors,parallel pipeline ADC,pipeline ADC architecture,pseudo-differential ADC
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