Single electron encoded logic memory elements

Lageweg, C.,Cotofana, S.,Vassiliadis, S.

Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference（2003）

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摘要

The ability to control the transport of individual electrons in Single Electron Tunneling (SET) based circuits creates the conditions for Single Electron Encoded Logic (SEEL). This paper investigates the implementation of SEEL memory elements. First, the threshold gate and the buffer/inverter are introduced, which serve as basic circuit blocks for the proposed memory element. Second, SEEL implementations of the RS-latch, D-latch and positive edge-triggered D flip-flop are proposed and verified by simulation. Finally, the area, switching delay and power consumption of the memory elements are compared with CMOS-like SET implementations.

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关键词

buffer circuits,flip-flops,integrated memory circuits,logic circuits,logic gates,power consumption,resonant tunnelling transistors,cmos,d latch,rs latch,buffer,inverter,memory elements implementation,positive edge triggered d flip flop,single electron encoded logic,single electron encoded logic memory elements,single electron tunneling based circuits,switching delay,threshold gate

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