A new inverse discrete wavelet packet transform architecture
ISSPA(2003)
Abstract
In this paper we present a new architecture and its scheduling algorithm for the 1-D inverse discrete wavelet packet transform. The proposed architecture is based on the classical recursive pyramid algorithm (RPA). We use two different RPA-modified blocks to compute three complete levels. We make use of folding and retiming techniques to improve the area and speed-rate. Two different implementations using lifting transformation and polyphase decomposition for the CDF2.2 biorthogonal wavelet coefficients are discussed. The lifting implementation requires approximately 45% less hardware resources than the polyphase structure. Finally, internal pipelining delays minimize the logic depth to one adder.
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Key words
wavelet packets,scheduling algorithm,hardware,computer architecture,signal analysis,wavelet packet transform
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