An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

Shien-Yang Wu,Lin, C.Y., Chiang, M.C.,Liaw, J.J.,J Y Cheng,Shao H Yang,S Z Chang, Manzhong Liang,T S Miyashita,C H Tsai,C H Chang,V S Chang, Y K Wu,J H Chen,H F Chen, K H Pan, R F Tsui,C H Yao, K C Ting, T Yamamoto,H T Huang,T L Lee,C H Lee,Weipin Chang,H M Lee,C C Chen,Tiansheuan Chang,R Chen,Y H Chiu,M H Tsai,S M Jang,K S Chen,Yuanchieh Ku

Electron Devices Meeting（2014）

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Abstract

Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additional 15% speed boost or 30% power reduction. Device overdrive capability is also extended by 70mV through reliability enhancement. Superior 128Mb High Density (HD) SRAM Vccmin capability of 450mV is achieved with variability reduction for the first time. Metal capacitance reduction by ~9% is realized with advanced interconnect scheme to enable dynamic power saving.

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Key words

CMOS integrated circuits,MOSFET,SRAM chips,copper,integrated circuit reliability,low-k dielectric thin films,Cu,HD SRAM Vccmin capability,advanced Cu-low-k interconnect,advanced interconnect scheme,device overdrive capability,dynamic power saving,enhanced 16nm CMOS technology,high density SRAM Vccmin capability,metal capacitance reduction,reliability enhancement,second generation FinFET transistors,size 16 nm,variability reduction

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