Simulation study of a new capacitor-less DRAM with Vertical Nanometer Pillar

Solid-State and Integrated Circuit Technology(2014)

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摘要
In this paper, a novel Vertical Nanometer Pillar structure of Double Gate (VNPDG) capacitor-less DRAM is proposed. The vertical pillar region provides an additional space which can store more excess holes to enhance kink effect easily. Thus, a longer retention time is derived by the virtue of the extend body region perpendicular to the electron inversion channel, which makes the excess holes not be recombined immediately. Combining the virtues of the device with applying the front-gate bias, we can optimize the driving force of drain bias and obtain that the retention time of the new structure is 4.9 × 103 times longer than that of the conventional structure.
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关键词
dram chips,vnpdg,capacitor-less dram,drain bias,dynamic random access memory,electron inversion channel,front-gate bias,kink effect enhancement,retention time,vertical nanometer pillar structure of double gate
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