A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel

Hyunbae Lee,T Song,Sangyeon Byeon,Kwanghun Lee,Inhwa Jung, Seongjin Kang,Ohkyu Kwon, Koeun Cheon,Donghwan Seol,Jongho Kang,Gunwoo Park,Yunsaing Kim

A-SSCC（2014）

引用 17|浏览19

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摘要

A 16.8Gbps/channel single ended transceiver for SiP based DRAM interface on silicon carrier channel is presented. A transmitter, receiver, and channel are all included in a single package. On the transmitter, 1 tap FFEs are used in 4:1 MUX and in output driver. On the receiver, source follower based CTLEs and self Vref generator are used for obtaining effective single ended signaling on Si-carrier channel. A BER that is less than 1e-12 is achieved in 65nm CMOS. The power efficiency of the transceiver is 5.9pJ/bit with 120Ω terminations at each transceiver side.

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关键词

cmos integrated circuits,dram chips,equalisers,system-in-package,transceivers,cmos,dram interface,sip,bit rate 16.8 gbit/s,continuous time linear equalizer,feed forward equalizer,multiplexer,silicon carrier channel,single ended signaling,single ended transceiver,size 65 nm,source follower,ber and 120ω terminations,ctle,ffe,self vref generator,sip based dram interface,sensors,silicon,bit error rate

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