Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology

Guansing Chen,Chinyang Wu,Chenlun Lin,Haowei Hung,Jri Lee

A-SSCC（2014）

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摘要

Fully-integrated 40-Gb/s pulse pattern generator (PPG) and bit-error-rate tester (BERT) chipsets has been presented in 65-nm CMOS technology. Using external clock inputs, the PPG and BERT achieve full operation with ultra-wide data range from 40 Mb/s to 40 Gb/s. Built-in PLL and CDR circuits are also included to provide robustness for standard specification testing.

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关键词

cmos integrated circuits,clock and data recovery circuits,error statistics,phase locked loops,pulse generators,test equipment,cdr circuits,cmos technology,pll circuits,bit error rate tester chipsets,bit rate 40 mbit/s to 40 gbit/s,external clock,fully integrated pulse pattern generator,size 65 nm,ultrawide data range,bit error rate,boosting,jitter,gain

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