Dielectric defects controlling instability in InGaAs n-MOSFETs with Al2O3/ZrO2 gate stack
VLSI Technology, Systems and Application（2014）
Abstract
Instability under positive bias stress (DC and AC) in InGaAs channel nMOSFETs with a a 1nmAl2O3/5nmZrO2 gate stack is studied. It is determined that the threshold voltage shift (ΔVT) during stress is primarily caused by a recoverable electron trapping at pre-existing defects, which are located pre-dominantly in the Al2O3 interfacial layer (IL). Generation of new electron trapping defects is found to occur in the IL, in the region close to the substrate, while trap generation in the high-k dielectric is negligible. The ΔVT recovery impacts the degradation dependency on the stress duty cycle and frequency.
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Key words
III-V semiconductors,MOSFET,alumina,electron traps,gallium arsenide,high-k dielectric thin films,indium compounds,stress analysis,zirconium compounds,Al2O3-ZrO2,IL,InGaAs,degradation dependency,dielectric defects,electron trapping defects,gate stack,high-k dielectric,instability control,interfacial layer,n-MOSFET channel,positive bias stress,size 1 nm,size 5 nm,stress duty cycle,threshold voltage shift,trap generation
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