A 93.4mm(2) 64gb Mlc Nand-Flash Memory With 16nm Cmos Technology

Solid-State Circuits Conference Digest of Technical Papers（2014）

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摘要

This paper presents a 64Gb MLC NAND-Flash memory fabricated with 16nm CMOS process technology to achieve high density and as small as 93.4mm2 die area. The chip consists of two planes of 1072 blocks each. A block consists of a string with 128 cells and a page size with 16KB and spare area for error-correction coding (ECC), totaling 4MB of capacity. The chip supports negative-level wordline drivability to increase cell Vth margin.

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关键词

CMOS memory circuits,NAND circuits,error correction codes,flash memories,logic testing,CMOS process technology,ECC,MLC NAND-flash memory,error-correction coding,size 16 nm

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