Development fine pitch area array Cu pillar/lead free solder bumps for large 28nm die in large organic flip chip packages

The viability of flip chip packages that incorporate small diameter (65um-80um) Cu pillar bumps on large die (up to 500mm2) in large packages (up to 55mm × 55mm) is demonstrated. To do so, bump formation and microstructure must be controlled. In particular, avoidance of bump tearing defects, which were found on assembly with die >410mm2, die > must be avoided. Fundamentally bump tearing results from uneven solidification because of temperature gradient in the assembly process during cool down, less than ideal solder volume, die pad - to - substrate pad offsets, increasing die size, and decreasing core thickness. These defects are further exaggerated by die designs that have regions of low and high bump density. Aided by finite element molding of the bump joints, a process was developed that eliminated tearing defects. The reliability of Cu pillar bumps on large die/package flip chip devices was also demonstrated using temperature cycling. In this work, both mechanical test die as well as active 28nm/40nm devices were evaluated. Thin core 45mm × 45mm packages containing ~250mm2 die using 65um diameter bumps passed 1500 cycles -55C to 125C with no signs of bump fatigue, die or package cracks. These devices had no bump tearing. Likewise, thick core 52.5mm × 52.5mm packages containing ~500mm2 die using 80um diameter Cu pillars were subjected to temperature cycling. In this case bump tearing was present to some minor degree on all devices. Packages with mechanical test die passes 1500 cycles with no signsof bump fatigue, whereas packages with active die passed 700 cycles with no signs of bump fatigue, die or package cracks.