Fabrication of strained Ge on insulator via room temperature wafer bonding

Ultimate Integration Silicon(2014)

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摘要
This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).
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关键词
ge-si alloys,chemical vapour deposition,etching,semiconductor growth,semiconductor materials,silicon-on-insulator,wafer bonding,geoi fabrication process,rpcvd,si0.66ge0.34,etch-back techniques,partially relaxed layer,reduced pressure chemical vapor deposition,room temperature wafer bonding,strained germanium on insulator fabrication,temperature 293 k to 298 k,silicon,surface roughness,rough surfaces,silicon on insulator
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