19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Mengfan Chang,Juijen Wu,Tunfei Chien,Yenchen Liu,Tingchin Yang,Wenchao Shen,Yachin King,Chorngjung Lin,Kufeng Lin,Yuder Chih,Sreedhar Natarajan,Jonathan Chang

Solid-State Circuits Conference Digest of Technical Papers（2014）

Cited 153|Views91

Key words

cmos integrated circuits,amplifiers,random-access storage,1t1r reram,cmos,dc current,reram,reram macro designs,sbwt,access time,battery powered devices,cell resistance,cell switch,compact cell area,conventional differential input vsa,cross point reram,energy harvesters,logic process compatibility,nonvolatile memory,resistive ram,self boost write termination scheme,size 28 nm,small sensing margin,storage capacity 1 mbit,swing sample and couple sense amplifier,time 404 ns,voltage 0.27 v to 1 v,voltage mode sense amplifier,wide set time distribution,write energy,write voltage

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