Power optimization technique of logic circuit based on distribution of energy

Power consumption in a digital circuit increases significantly during test mode. The paper proposes a novel technique to minimize the peak power by circuit clustering based on distribution of energy among the scan cells. All the clusters are equally compatible with respect to the number of scan cells and total system energy which is equally divided among the clusters. The final energy of the system becomes substantially lower than the initial energy of the system. This leads to an optimal solution for the clustering algorithm. A polynomial time algorithm is proposed for clustering the circuits. The results for ISCAS89 sequential benchmark circuits show that the proposed method ensures a significant reduction of power consumption in larger circuits at the cost of significantly less overhead as compared to those of the earlier methods.