A 23mW/lane 1.2–6.8Gb/s multi-standard transceiver in 28nm CMOS

Seongho Lee,D Tran,Tamer Ali,Burak Catli,Heng Zhang,Wei Zhang,Mohammed Abdullatif,Zhi Huang,Guansheng Li,Mahmoud Reza Ahmadi,Afshin Momtaz

A-SSCC（2014）

引用 3|浏览33

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摘要

This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2-6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI. Power consumption per lane is 23mW at 0.9V for SATA3 at 6Gb/s, with an area of 0.265mm2 for a single-lane transceiver with PLL.

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关键词

cmos integrated circuits,low-power electronics,phase locked loops,radio transceivers,cmos technology,pcie,pll,qsgmii,rxaui,sata,sgmii,usb3,xaui,bit rate 1.2 gbit/s to 6.8 gbit/s,circuit technique,communication standards,low-power multistandard transceiver design,power 23 mw,power consumption,single-lane transceiver,voltage 0.9 v,clock and data recovery,high speed integrated circuits,serializer-deserializers,transceivers,jitter

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