Redundant Circuits With Latchup Protection

2013 IEEE 20TH INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS)（2013）

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摘要

The paper presents triple and double modular redundant (TMR and DMR) circuits with the latchup protection. Additional logic has been designed to control the latchup protection phase and different power domains. An analytical model for the failure-free probability estimation has been developed too. Test circuits have been implemented and simulated.

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关键词

Fault tolerance,triple and double modular redundancy,latchup protection,ASIC design

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