A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout

A compact two-step 5b logarithmic ADC is designed for the readout application of multi-level cell phase-change memory (PCM). A bleeding-current-assisted regulated-cascode stage accurately converts the wide-dynamic range resistance of a PCM cell into a current. The designed ADC is composed of a logarithmic 2b current-mode flash ADC as a coarse ADC and a logarithmic 3b time-to-digital converter as a fine ADC with redundancy, resulting in compact size and low power consumption. The minimum step-size of the ADC is 0.1% of the full scale and the conversion time is 100 ns. The chip was fabricated in a 65 nm CMOS and the width of a single channel ADC is 15 μm. Single-channel ADC consumes 108 μW at 10 MS/s conversion rate under a 1.2 V supply.