Device Technology for embedded DRAM utilizing stacked MIM(Metal-Insulator-Metal) Capacitor

Yasushi Yamagata,Hiroki Shirai,Hirotoshi Sugimura,S. Arai,Tomoko Wake,Ken Inoue,Takashi Sakoh,Masato Sakao,Takaho Tanigawa

CICC（2006）

Cited 9|Views9

No score

Abstract

This paper presents embedded DRAM device technology utilizing stacked MIM(metal-insulator-metal) capacitor. Targeted for high random-access performance as well as low-power data-streaming applications, original structure named "full metal DRAM" has been devised and implemented from 150nm generation. This features reduced parasitic resistance of DRAM cell and fully-compatible CMOS Trs. characteristics with that of leading-edge CMOS. In 90nm generation, ZrO 2 is introduced as capacitor dielectric material for cell size reduction. For the next generation of 55nm, high-k gate dielectric(HfSiON) will be introduced in CMOS platform, which can be effectively exploited for embedded DRAM scaling and performance improvement

Translated text

Key words

zro2,device technology,low power data streaming,cmos integrated circuits,90 nm,high-k dielectric thin films,hfsion,parasitic resistance,high-k gate dielectric,55 nm,high random access performance,mim devices,low-power electronics,dram chips,capacitors,mim capacitor,cmos platform,capacitor dielectric material,zirconium compounds,150 nm,cell size reduction,hafnium compounds,embedded dram,random access,low power electronics

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined