A universal framework of dual-use model for both performance and functionality based on the abstract state machine

Xie Zheng,Wang Xin'an,Lian Zhibin,Li Qiuping,Yong Shanshan

Proceedings of International Conference on ASIC（2013）

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Abstract

Confronted with ever increasing design complexity, modeling system architectures for early performance evaluation and fast exploration of the design space will be a necessary process. Meanwhile, function verification has been a bottleneck for time to market. The sharing of the two processes will greatly enhance the efficiency of system development. This paper presents a universal framework of dual-use model for both performance and functionality based on the abstract state machine, to reuse the performance model in building reference model to reduce the cycle of verification. The Application Program Interface (API) function library based on Universal Verification Methodology (UVM), corresponding to the dual-use model, is provided simultaneously. Associated with the function library, the abstract state machine is recorded by the state machine component in Verification Expert System (VES) toolbox to generate specific code automatically. © 2013 IEEE.

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Key words

application program interfaces,electronic engineering computing,expert systems,finite state machines,formal verification,UVM,abstract state machine,application program interface function library,design complexity,design space exploration,dual use model,model reuse,reference model,state machine component,universal verification methodology,verification cycle reduction,verification expert system toolbox,

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