Co-design of ESD protection and LNA in RFIC
ASICON（2013）
Abstract
This paper introduces a new FoM (figure of merit) to evaluate the overall performance of ESD and LNA and presents a design procedure of establishing a standard library of ESD protection cells to reduce the design time and complexity for RFIC designer. The electrostatic discharge protection cells have been designed in a 0.35μm BiCMOS process. The ESD robustness and RF characteristics will be verified when the RF chip is done.
MoreTranslated text
Key words
lna,low noise amplifiers,rfic,bicmos analogue integrated circuits,radiofrequency integrated circuits,figure of merit,esd protection,size 0.35 mum,electrostatic discharge protection,integrated circuit design,electrostatic discharge,bicmos process,fom
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined