Fault-tolerant TMR and DMR circuits with latchup protection switches.

•The ASIC design flow is modified to protect circuits from the single event effects.•The protection switch is verified by measurements in radiation environment.•TMR and DMR shift-registers with latchup protection are designed and tested.•DMR with protection switch outperforms TMR in terms of failure-free probability.•The fault-tolerant DMR middleware switch processor is designed and implemented.