Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

IEEE Trans. on CAD of Integrated Circuits and Systems(2015)

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摘要
We enhance the capability of industry standard compact model BSIM6 to model the parasitic current Iedge at the STI edge. Accurate, efficient and scalable model for Iedge is developed by finding the key differences between Iedge and main device drain-current (Imain). It is found that Iedge has a different sub-threshold slope, body-bias coefficient and short-channel behavior as compared to Imain. These important effects along with their dependencies on device geometry, bias conditions and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.
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关键词
analog technology,bsim6,compact models,parasitic currents,sti edge effects
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