Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs

An improved analytical model for flicker noise (1/f noise) in MOSFETs is presented. Current models do not capture the effect of high trap density in the halo regions of the devices, which leads to significantly different bias dependence of flicker noise across device geometry. The proposed model is the first compact model implementation capturing such effect and show distinct improvements over other existing noise models. The model is compatible with BSIM6, the latest industry standard model for bulk MOSFET, and is validated with measurements from 45nm low power CMOS technology node.