An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy and Performance in Reconfigurable NoC Architectures

In this paper, an efficient application mapping approach is proposed for the co-optimization of reliability, communication energy and performance in network-on-chip (NoC) based reconfigurable architectures. A cost model for the co-optimization of reliability, communication energy and performance (CoREP) is developed to evaluate the overall cost of a mapping. In this model, communication energy and latency (as a measure of performance) are first considered in energy latency product (ELP), and then ELP is co-optimized with reliability by a weight parameter that defines the optimization priority. Both the transient and intermittent errors in NoC are modeled in CoREP. Based on CoREP, a mapping approach, referred to as priority and ratio oriented branch and bound (PRBB), is proposed to derive the best mapping by enumerating all the candidate mappings organized in a search tree. Two techniques, branch node priority recognition and partial cost ratio utilization, are adopted to improve the search efficiency. Experimental results show that the proposed approach achieves significant improvements in reliability, energy and performance. Compared with the state-of-the-art methods in the same scope, the proposed approach has following distinctive advantages: 1) CoREP is highly flexible to address various NoC topologies and routing algorithms while others are limited to some specific topologies and/or routing algorithms; 2) General quantitative evaluation for reliability, energy and performance are made respectively before integrated into unified cost model in general context while other similar models only touch upon two of them; 3) CoREP based PRBB attains a competitive processing speed, which is faster than other mapping approaches.