A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-Type) 3-D NAND

The 3-D NAND flash is a path to achieve the highest density and the lowest cost of solid-state nonvolatile memory. Vertical gate type 3-D NAND, one of the 3-D NAND flash memories, has the smallest cell footprint (4F2). We had previously proposed a split page design for selecting NAND strings that incurs an array overhead. In this letter, we propose a new decoding method, using two stagger select string lines to select each NAND string. It greatly reduces the overhead and thus improves efficiency. The array block efficiency after improvement is close to that of conventional 2-D NAND (~ 80 %).