3D Stacked DRAM Refresh Management with Guaranteed Data Reliability

The three-dimensional (3D) integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for the 3D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.