Design optimization of CMOS CDC comparators

Mingzhen Wang,Hongxi Xue, Gang Yang,Yingjian Wu

Computational Problem-Solving（2011）

Cited 8|Views9

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Abstract

This paper presents design of CMOS CDC-based comparators with an optimum method to suppress dynamic offset for high-speed flash ADCs. The CDC-based comparators are introduced, analyzed, modeled and optimized. The experiment results have verified the design optimization. Compared to the ADCs with random sizing CDC comparators, the dynamic performance in terms of SNR and SFDR has improved over 30% @ the signal frequency lower than 800MHz and over 140% @ the signal frequency higher than 800MHz.

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Key words

analogue-digital conversion,circuit optimisation,sfdr,high-speed integrated circuits,clocks,spurious-free dynamic range,clocked digital comparator,integrated circuit design,comparators (circuits),cmos digital integrated circuits,snr,high-speed flash adc,dynamic offset suppression,cmos cdc comparator design optimization,capacitance,switches,quantization,threshold voltage,transistors,mathematical model,design optimization

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