Impact of gate dielectric geometry on the nanowire MOSFETs performance and scaling

In this paper, we discuss the unique property of electrostatics in the gate dielectric of the cylindrical nanowire (NW) MOSFETs, and its impact on the transistor performance and scaling, particularly on the gate tunneling leakage. A dielectric curvature parameter theta = T-OX/R-s with dielectric physical thickness T-OX and NW radius R-s is introduced. (1) A 2D tunneling model is developed and used to assess the tunneling rate reduction in cylindrical gate (CG) in NW transistor comparing with the planar gate (PG) double gate (DG) transistor. This effect can be very significant when theta is large in the practical NW devices. High-k gate dielectric is more effective to suppress the gate leakage in NW than in PG transistors, since High-k dielectric not only increases T-OX, but also increases theta, both reduce the tunneling rate. (2) On the other hand, comparing NW with radius R-s and DG-PG transistor with body thickness T-semi = 2R(s), the carrier quantization induced tunneling barrier reduction is larger in NW than in DG-PG transistors. For n-MOSFETs, the lowest conduction valley transition effect between Gamma, L, and Delta (or X) valleys should also be considered due to carrier quantization in the channels. The gate tunneling rate is finally determined by combining two effects of (1) and (2). Different results due to different conduction band structures are demonstrated for Si, Ge, and InGaAs NWs respectively. (3) The overdrive gate voltage in NW transistor can be reduced significantly, comparing with PG transistor with the same T-OX. (4) For the device reliability assessment, at the same time evolution of dielectric charge generation, the NW transistor lifetime can be extended by as much as one order or more, comparing with the PG transistor with the same T-OX, when theta is large.