A 16-Bit, 250ksps Successive Approximation Register Adc Based On The Charge-Redistribution Technique

This paper presents a 16-bit 250ksps successive approximation register analog-to-digital converter (SAR-ADC) based on the charge-redistribution technique. The ADC contains a charge-redistribution DAC, a high precision internal voltage reference, a low offset comparator and a serial data interface. The split capacitor array was used to save the area of the chip and improve the speed and accuracy of the ADC. The electrical programming fuse (Efuse) which can be demonstrated after package without any extra pads or special equipments required is employed to optimize the performance of reference voltage and internal DAC. Measured at +5V supply and 250ksps, and consumes current of less than 17mA. The experimental measurement results indicate that an SNR of 88.8 dB, typical DNL of 0.6LSB and INL of 2.5LSB were achieved. The prototype was fabricated in a commercial 2P3M CMOS technology with the feature size of 0.6 mu m and occupies an active area of 4.2mm*5.2 mm.