Reliability simulation of metal bump in a three-dimensional chip stacking structure

In order to adapt the development of the Integrated circuit, a three-dimensional chip stacking structure was developed to achieve high performance, low power consumption and small packaging size. The 3D structure was divided into four major parts, including through silicon via, isolation wall, conductive line, and metal bump. We focused on the reliability of the metal bump in this kind of three-dimensional chip stacking structure. However, the strain and the stress were difficult to be detected during the temperature cycling. Simulating and analyzing with the software ANSYS was an appropriate method. In this paper, we used the software ANSYS to simulate and analyze this 3D chip stacking structure in order to find out the dangerous point during the temperature cycling. © 2010 IEEE.