Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology
Electron Devices Meeting（2009）
摘要
In this paper, the characteristic variability in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) is experimentally studied. Variation sources in SNWTs are extracted for the first time, taking into account the strongly-confined geometry induced quantum effect, quasi-ballistic effects, as well as the parasitic quantum resistance at the interface of 1D channel and 3D wide S/D regions. The measured results show that with suppressed random dopant fluctuations (RDF) in the intrinsic channel, variations in radius (R) and metal-gate work function (WF) of SNWTs dominate both the threshold voltage and on-current fluctuations, and line-edge-roughness (LER) shows minor impact. The influence of the SNWT variation sources on SRAM performance is estimated and compared with planar devices. In addition to process variation, variation induced by random telegraph signal (RTS) noise in SNWTs is also investigated for the evaluation of SRAM cell operating window. Design optimization guidelines are given based on the SRAM variation analyzed results.
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关键词
cmos integrated circuits,intrinsic channel,random telegraph signal noise,quasiballistic effects,silicon nanowire cmos technology,metal gate work function,nanowires,metal-oxide-semiconductor field effect transistors,characteristic variability,sram performance,sram variation,sram cell operating window,static random access memory,design optimization guidelines,geometry induced quantum effect,gate-all-around silicon nanowire mosfet,parasitic quantum resistance,mosfet,line edge roughness,suppressed random dopant fluctuations,complementary metal-oxide-semiconductor,work function,design optimization,resource description framework,quantum effect,silicon,logic gates,threshold voltage,process variation,complementary metal oxide semiconductor,solid modeling,fluctuations
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