Hierarchical Timing Analysis Considering Global False Coupling Interaction

In today's deep-submicron technologies, neighbouring line switching can contribute to a large portion of the delay of a line. A hierarchical design is unavoidable because of a huge circuit size. It becomes more important how we can consider hierarchically meaningful structure in circuit delay analysis. To improve accuracy in hierarchical timing analysis, in this paper we inject the notions of local false coupling interaction and global false coupling interaction, and then propose a comprehensive approach to identify valid interaction using functional relations considering global false coupling interaction generated by connections between modules. Experiments on ISCAS-85 benchmark circuits show the value of considering the global false coupling interaction to reduce the excessive conservatism during hierarchical timing analysis.