A Fully Integrated 1.2-Ghz Cmos Phase-Locked Loop

2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2（2005）

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摘要

A 1.2GHz phase-locked loop (PLL) is designed in a 0.18um 3.3V 1P6M CMOS RF technology. The PLL consists of a LC-tank circuit, prescaler, frequency divider, frequency/phase detector, charge pump that includes a bandgap current reference and a passive loop filter. The passive loop filter is also on-chip and no off-chip components are needed.

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关键词

phase-locked loop, VCO, prescaler, charge pump, bandgap current reference, frequency divider

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