Npu Asic Chip Tester

PROCEEDINGS OF THE FOURTH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY（1995）

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Abstract

NPU ASIC chip tester is a low cost, functional tester. It can test chips in three modes: off-line, on-line, interactive. It can test chips that have up to 128 pins. Each test driver of this tester is programmable independently. Its hardware is implemented mainly using Xilinx FPGAs. It has a powerful software package, which facilitates the design of test programs and the analysis of test results. This software package also provides interfaces with many current EDA tools.

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Key words

interface,functional testing,chip,computer architecture,system testing,application specific integrated circuits,software testing,cost function,eda tools

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