A 3-transistor CMOS active pixel with in-pixel correlated double sampling

Shaohua Liu,Lai Jiang,Hang Yu,Yan Li,Daoming Xi,Qingguo Xie

Electron Devices and Solid-State Circuits（2013）

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摘要

This paper presents a 3-transistor CMOS active pixel structure with in-pixel correlated double sampling. Designed in a standard 0.18 μm CMOS process, the structure effectively suppresses temporal noise and fixed pattern noise (FPN), thanks to the shared correlated double sampling circuit inside the pixel. Fill factor is also improved while maintaining pixel performance. Validation by Spectre simulator shows that the proposed structure suppresses 100 mV input offset to the microvolt range, and the pixel readout time is ~90 ns. The average power consumption of each pixel is 18 μW.

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关键词

cmos process,transistor circuits,cmos image sensors,transistor cmos active pixel structure,correlation theory,spectre simulator,correlated double sampling,size 0.18 mum,cmos active pixel,integrated circuit noise,fill factor,temporal noise suppression,fixed pattern noise,fpn suppression,interference suppression,in-pixel correlated double sampling circuit,shared pixel structure,power 18 muw,cmos integrated circuits

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