A tri-level parallel architecture for NAND flash storage system

Because of its lightweight, high density, and energy-efficient characteristics, NAND flash memory has been widely used as a storage medium for electronic devices in multiple areas, such as industrial electronics, biomedical image recorder and computers. However, due to its low IO performance and long operation latency, multiple techniques are applied to the NAND storage systems to overcome these drawbacks. In this paper, we present a tri-level parallel architecture to improve the bandwidth of the storage system by hiding the operation latency through controller level, chip level and die level interleaving. The evaluation results implemented on a prototype board show that the read and write throughput of the system based on the proposed architecture could be improved enormously by utilizing multiple level interleaving techniques, and the redundancy of the flash bus could be eliminated maximally.