An enhanced area-efficient on-chip compensation technique for power converters
Electron Devices and Solid State Circuit（2012）
Abstract
A novel high area-efficient on-chip lag (PI) compensation technique for power converters is proposed in this paper. This technique combined current-mode with voltage-mode capacitor multiplier. The compensation capacitor can be reduced to smaller than 10% of the conventional one. This proposed technique is successfully verified by a boost converter system with current program mode (CPM) control. The system proves to be stable for loading conditions from 100mA to 300mA. While conventional compensation capacitor and resistor are 30pF and 2.5MΩ, the proposed technique needs only 3pF and 1.2MΩ consuming 8μA extra current.
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Key words
power convertors,resistor,dc-dc converterr,capacitance 3 pf,type ii compensator,enhanced area-efficient on-chip lag compensation technique,dc-dc power convertors,pi compensation,cpm control,power converters,capacitance 30 pf,voltage multipliers,current program mode control,voltage-mode capacitor multiplier,capacitors,current 8 mua,combined current-mode capacitor multiplier,pi compensation technique,current 100 ma to 300 ma,capacitor multiplier,compensation capacitor,resistance 1.2 mohm,resistance 2.5 mohm,compensation,on-chip compensation
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