Optimization of 40-nm Node Epitaxial Diode Array for Phase-Change Memory Application
Electron Device Letters, IEEE（2012）
Abstract
A numerical model of an epitaxial (EPI) diode array for next-generation memory device application, including phase-change memory, has been presented. According to a diode array process scheme and technology computer-aided design (TCAD) simulation results, a quasi-physical model with a buried n+ layer dosage, EPI layer thickness, and breakdown voltage (BVD) correlation is proposed to improve electrical performance. From the optimal silicon-based results, a 16×16 diode array shows a drive current density of ~56.6 mA/μm2, a BVD of ~8 V, a Jon/Joff ratio of ~109, and crosstalk immunity. Additionally, this calibrated physical model can be applied in the next generation of silicon-based fabrication with parameters extraction.
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Key words
phase-change memory (pcm),electrical performance improvement,epitaxial diode array,silicon-based fabrication,buried $hbox{n}^{+}$ layer (bnl) series resistance,bvd,buried n+ layer dosage,tcad simulation,numerical model,quasiphysical model,parameters extraction,phase change memories,breakdown voltage correlation,technology cad (electronics),numerical analysis,size 40 nm,phase-change memory application,epitaxial (epi) diode array,epi layer thickness,silicon,next-generation memory device application,si,elemental semiconductors,crosstalk immunity,buried n + layer (bnl) series resistance,technology computer-aided design simulation,electric breakdown
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