Rail-to-rail digital to analog converter with shared binary weighted resistive load interpolation.

This paper presents a binary-weighted resistive load interpolation digital-to-analog converter (RIDAC) architecture with improved resolution performance. The RIDAC consists of coarse resistor string DAC driving a multi-input operational amplifier where the interpolation is performed inside the load branch of this amplifier. The shared resistive load provides an accurate and monotonic binary-weighted interpolation between coarse voltage levels with reduced number of resistors. The measured integral non-linearity (INL) and differential nonlinearity (DNL) are 0.68 LSB and 0.35 LSB, respectively. The chip occupies 0.042 mm(2) area and consumes 1.44 mW static power from a 1.8 V power supply.