Increased Rate of Multiple-Bit Upset From Neutrons at Large Angles of Incidence
Device and Materials Reliability, IEEE Transactions（2008）
Abstract
Neutron interactions with terrestrial systems produce soft errors, increasing the failure-in-time (FIT) rate of advanced CMOS circuits. These neutron-induced errors are a critical reliability problem facing advanced technologies. This paper reports the accelerated neutron testing on a 90-nm CMOS SRAM that exhibits an increased multiple-bit upset FIT rate from neutrons at large angles of incidence. The modeling of these data is used to predict the reliability of ground-based systems.
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Key words
CMOS memory circuits,SRAM chips,integrated circuit reliability,neutron effects,CMOS SRAM,failure-in-time rate,ground-based systems,incidence angles,modeling,multiple-bit upset,neutron testing,reliability,size 90 nm,Multiple-bit upset (MBU),neutron,soft error
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