A Broadband Chip-Level Power-Bus Model Feasible for Power Integrity Chip-Package Codesign in High-Speed Memory Circuits
Electromagnetic Compatibility, IEEE Transactions（2010）
Abstract
Based on two-port measurements, a distributed compact model and an extraction method for the power bus of a high-speed memory chip are proposed. The 1-D model is constructed according to the relative locations of the power and ground pads on the chip. The power bus around each power or ground pad is modeled by a section of resistor-inductor-capacitor (RLC) T-model, and the complete distributed model is formed by cascading all the T-model sections. The T-model at each section can be extracted through the measured two-port Z-parameters by using the Powell's optimization method. Because the model is extracted from measured data, detailed (or proprietary) chip-layout information is not necessary. Another advantage is this compact model keeps the broadband accuracy by the distribution concept and is easy to link with the package model for the power integrity codesign.
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Key words
optimisation,extraction method,power distribution network,resistor-inductor-capacitor t-model,1d model,integrated circuit modelling,ground pad,power integrity (pi),rlc circuits,distributed compact model,rlc t-model,z-parameters,dram chips,ddr sdram chip,high-speed integrated circuits,power integrity chip-package codesign,two port measurement,ground bounce noise,integrated circuit noise,integrated circuit design,electromagnetic compatibility,optimization method,chip scale packaging,double data rate synchronous dynamic random access memory,high speed memory circuits,broadband chip level power bus model,chip,computational modeling,data mining,capacitance,system on a chip,layout
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