Methodology for I/O cell placement and checking in ASIC designs using area-array power grid

Patrick H Buffet, Joseph Natonio,Robert A Proctor, Y H Sun,Gulsun Yasar, Sun, Yu.H.

Orlando, FL（2000）

Cited 31|Views11

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Abstract

Electrical rule checking is fundamental to achieve a good I/O cell placement. This paper presents the analysis techniques used to design a robust power-grid structure, the method used to make I/O cell placement guidelines, details of the I/O cell placement process and electrical checking algorithms

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Key words

application specific integrated circuits,cellular arrays,circuit layout CAD,integrated circuit layout,logic arrays,ASIC designs,I/O cell placement,analysis techniques,area-array power grid,electrical checking algorithms,electrical rule checking,robust power-grid structure

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