Simulation of Layout-Dependent STI Stress and Its Impact on Circuit Performance
San Diego, CA（2009）
摘要
The impact of STI stress with layout dependency on circuit performance is investigated. A 3D stress simulator has been developed using finite element method, which considers both the layout design and process information (PDK). The mobility change due to stress is included in the transistor modeling for circuit simulation. The circuit performance can thus be analyzed with nonlocal stress. As a test case, a buffered SR flip-flop was simulated with and without STI stress considered. It can be seen that STI stress has non-negligible influence on the circuit performance.
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关键词
semiconductor device models,cmos integrated circuits,layout design,stress analysis,nonlocal stress,mobility change,layout-dependent sti stress simulation,3d stress simulator,finite element method,finite element analysis,semiconductor process modelling,transistor modeling,flip-flops,cmos devices,integrated circuit layout,circuit performance,mosfet,buffered sr flip-flop,shallow trench isolation,stress effects,isolation technology,layout,silicon,strontium,stress,transistors
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