A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
ISSCC(2011)
Abstract
Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utilizing data bus inversion, error-detection coding, data training and channel equalization. However, channel crosstalk is becoming a major barrier to further speed improvement. A common solution for channel crosstalk reduction at the system level is to use a shielding line or wide spacing between signal lines, but increasing the number of layers in a chip package and PCB increase system cost. To remove the shielding lines and increase speed, this paper presents a channel crosstalk equalizer with programmable signal ordering capability for the DRAM transmitter. In addition, this paper addresses tri-mode clocking to reduce the system jitter for better timing margin: PLL off, LC-PLL and injection-locked oscillator.
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Key words
channel crosstalk,data training,error-detection coding,chip package,lc-pll,gddr5 sdram,size 40 nm,pcb,dram chips,clocks,phase locked loops,programmable dq ordering crosstalk equalizer,dram transmitter,printed circuits,channel equalization,pll off,injection-locked oscillator,system jitter reduction,equalisers,tri-mode clocking,adjustable clock-tracking bw,memory size 2 gbyte,data bus inversion,crosstalk,injection locked oscillator,jitter,phase lock loop
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