DeNovo: Rethinking Hardware for Disciplined Parallelism

We believe that future large-scale multicore systems will require disciplined parallel programming practices, incl ud- ing data-race-freedom, deterministic-by-default semant ics, and structured, explicit parallel control and side-effect s. We argue that this software evolution presents far-reachin g opportunities for parallel hardware design to greatly im- prove complexity, power-efficiency, and performance scal- ability. The DeNovo project is rethinking hardware design from the ground up to exploit these opportunities. This paper presents the broad research agenda of DeNovo, in- cluding a holistic rethinking of cache coherence, memory consistency, communication, and cache architecture.