Deep-submicron CMOS technologies for low-power and high-performance operation

Integrated circuits with 1GHz logic, 1G bit DRAM, and 1G transistors, together with the CMOS technology with a gate length of less than 0.2 mu m are the ingredients of the "Giga-Era." However, in order to integrate these billions of MOSs at giga-frequencies, the problem of the power consumption cannot be avoided. It is a common practice to cope with this problem by reducing the power supply voltage. In deep submicron MOS, although the basic gate delay is not likely to degrade as the power supply voltage is reduced, it is necessary to set a low threshold value (V-th) within the wafer plane with reduced parasitic devices, if the absolute current values become important, as in the interconnect load. However, reliability problems involving the short-channel effect and hot carriers then cannot be avoided. This paper describes the use of the cobalt silicide process and shallow extension structure of the source/drain to reduce the parasitic resistance. It is also shown that setting a low V-th with fewer fluctuations is possible by combining the double-side-wall process and the counter-dose process. By means of the above process, deep submicron CMOS with low parasitic resistance and low V-th can be fabricated.